Commentary Luca Larcher

3D Integration of Novel Memory Devices: an Opportunity for Profound Innovations in Digital Integrated System Architecture   Luca Larcher   University of Modena   Email: luca.larcher@unimore.it

In this commentary I want to share some ideas and discuss the future evolution of digital integrated system architecture from the standpoint of the new opportunities enabled by the 3D integration of novel non-volatile memory devices.

The digital consumer electronics drives today much of high-technology research and products that have major impacts on our society and life. Since the invention of integrated circuit in the 60s, the evolution of the mainstream CMOS technology have been dominated by the scaling down of transistor sizes, which are approaching today the 20 nanometer limit. Despite future transistors integrating novel materials and novel device architecture (e.g. Finfet, SOI) may have minimum features as small as 5 nanometers, the device variability (due the very small number of atoms and electrons involved in device operations) will represent a tremendous obstacle for a full industrial exploitation, determining, in the best scenario, a huge cost increase for the technology development.

In this scenario, the 3D integration is an attractive option to increase the number of transistors per chip up to 100 billion and beyond, thus overcoming the limit of planar scaling and allowing the system complexity required by future high-performance digital applications. Despite the 3D integration is not a novel concept (e.g. integrated circuits are used to be stacked using Through-Silicon-Via (TSV) technology in a SiP fashion), the strong effort pursued today by the major memory chip-maker companies toward the 3D integration of novel non-volatile memory devices (e.g. charge-trapping Flash, resistive RAM) represents an extraordinary opportunity to explore the real potential of 3D integrated system architectures.

In fact, the development of vertical charge-trapping NAND Flash devices requires to address crucial issues (e.g. conductivity of polycrystalline device channel, high dielectric quality with low-temperature process) that will open the way also for the 3D realization and integration of logic devices. New opportunities are also connected to emerging non-volatile memory devices such as resistive RRAMs, which have been the subject of very intense research in the last decade. A RRAM device consists basically in a selector (e.g. transistor) connected to a MIM capacitor, which exploits the resistive switching observed on many binary/ternary transition-metal oxides after an initial operation called forming. RRAM devices, also called "memristor", can be used as both memory and logic devices, thanks to their capability to store and process information at the same time. This feature, enabling the realization of hybrid CMOS system architectures (e.g. logic-in-memory array), is extremely interesting to explore biology-inspired digital architecture resembling brain synapses. In addition, RRAM devices are very suited to 3D integration, representing an ideal building block for 3D integrated digital systems.

Unfortunately, there are several issues preventing the full industrial exploitation of the RRAM concept that concern the device variability (both intrinsic and operations-related), the selector, the scaling tradeoffs with power consumption, noise, and retention. To solve such issues, the understanding of the physical mechanisms governing device operations is crucial, which requires novel atomic-model simulations connecting the material properties to the ultimate electrical performance of the device. The development of simulation models, which should allow both predicting device performance and reproducing statistical measurements, represents a very attractive multi-disciplinary research opportunity, combining atomic- and device-level modeling to physical/electrical characterization. Such topics will be discussed in my presentation.