Digital Design and Computer Architecture in the Era of System on Chip (SoC) and Internet of Things (IoT)

Chairs: Yuri Panchul and Stanislav Shidlovsky

The workshop program (in Russian) consists of 5 days the symposium-seminar and 5 days of the school-training.

Tutorial book from the Digital Design workshop will be published in Russian. For details, click here, and to download format sample, click here.

The workshop will involve its participants in the task of building the educational infrastructure for the future of Russian microelectronics. The organizers will present the educational programs originated in Imagination Technologies (the company that designed PowerVR GPU inside Apple iPhone), Radeon Technology Group of Advanced Micro Devices, and University of California Santa Cruz Extension in Silicon Valley. The lectures will be structured to show the path from student projects and research activities to popular devices in consumer electronics, automotive and airspace industries. The participants will have an opportunity to experiment with prototyping system on chips using boards with Field Programmable Gate Arrays (FPGAs) during hands-on exercises. The subtopics of the workshop will include:

• Setting up the basic education in digital design in a university using Nanometer ASIC program, with the focus on RTL-to-GDSII flow, the mainstream design methodology for the past 25 years;
• Improving university curriculum in embedded microcontrollers with Connected MCU course that links the traditional microcontroller subjects with computer architecture and RTOSes;
• Exploring topics for the research projects in processor microarchitecture and heterogeneous computing, using MIPSfpga industrial IP core and FPGA boards;
• Path to productize the research prototypes of chips for Internet of Things (IoT) using Imagination Oberon platform and Europractice IC services;
• Discussion of how the market shapes the offerings in licensable processor IP market using MIPS cores from Imagination Technology as examples;
• Real cases of Russian microelectronic projects that use the discussed technologies, namely Baikal Electronics, ELVEES-NeoTek, MRI Progress and Lab Systems;
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• General-purpose computing meets graphic processors, what it means for high-performance software, VR, AR and AI applications

For sample slides of the workshop speaker, Charles Dancak, click here

For previous nanometer scale ASIC seminars information, click here

Presenters include:

• Sergey Brazhnikov, Scientific-Manufacturing Complex "Technological Centre", Zelenograd, Russia
  Master-slice Semicustom VLSI Design Flow by Means of “Kovcheg” CAD: Introduction to SystemVerilog
• Charles Dancak, University of California Santa Cruz, Santa Cruz, California, USA
  The Nanoscale Application-Specific Integrated Circuit (ASIC) Development Process
• Boris Ivashinnikov, Komsomolsk-na-Amure State Technical University, Komsomolsk-na Amure, Russia
  Intergration into MIPS: A Simple Text Terminal with Output via VGA Interface
• Alexander Kamkin, Institute for the System Programming of the Russian Academy of Sciences, Moscow, Russia
  A MicroTESK-based Test Program Generator for MIPS Microprocessors
• Ilya Kudryavtsev, Samara National Research University, Samara, Russia
  HDL Application for Digital Synthesis in FPGA and
  Teaching students FPGA, DSP and microcontrollers in Samara University
• Vladimir Mikerin, Novosibirsk State Technical University, Novosibirsk, Russia
  Cluster Approach in Education: From Transistor to FPGA
• Anton Moiseev, Nizny Novgorod State Technical University, Nizny Novgorod, Russia
  Digital Electronics for Mathematicians and Programmers
• Timour Paltashev, Northwestern Polytechnica University, Fremont, California, USA
  AMD Exoscale Supercomputers Strategy
• Yuri Panchul, Imagination Technologies, Sunnyvale, California, USA
  Digital Design and Computer Architecture in the Era of System on Chip (SoC) and Internet of Things (IoT)
• Evgenii Primakov and Alexander Silantiev, National Research University of Electronic Technology, Zelenograd, Russia
  Implementation of Wishbone as System Bus for MIPSfpga
• Nikita Polyakov, Moscow Institute of Physics and Technology, and JSC MCST Moscow, Russia
  Teaching Students in Basics of Digital Device Design on FPGA in Moscow Institute of Physics and Technology
• Stanislav Zhelnio, Gazprom Inform, Moscow, Russia
  Introduction into SoC: Building an fpga-based System by Integration of MIPSfpga Processor Core with Memory and Peripheral Devices Using AHB-Lite Bus

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